Program at a Glance


Tutorials: Monday, 14 September 2026 (free for all AICAS participants)
Venue: 144 Xuan-Thuy Road, Cau Giay Ward, Hanoi, Vietnam

9:00:00 AM-9:15:00 AM

Opening Session
Room: 1st Floor,  Jonathan KS Choi Culture Center, VNU Hanoi

9:15 AM-6:00 PM

Tutorial #1: AI-Enabled IC Design Automation and Intelligent Hardware Architectures
Chairs: Minh-Thuy Le, HUST, Vietnam
Quang-Kien Trinh, LQDTU, Vietnam
Room: 1st Floor,  Jonathan KS Choi Culture Center, VNU Hanoi

Tutorial #2: High-Speed Interconnect and Clock Circuits for AI Computing Infrastructures
Chairs: Du Yuan, Nanjing University, China;
Duc-Tho Mai, ACT, Vietnam
Room: 2nd Floor, Jonathan KS Choi Culture Center, VNU Hanoi

9:15 AM - 10:15 AM

Hardware-Assisted Verification for Next-Generation AI Hardware Accelerators
Ibrahim Elfadel, Khalifa University, United Arab Emirates

Introduction to High-Speed SerDes Communications
Quan Pan, Southern University of Science and Technology, China

10:15 AM

Tea Break (15 minutes)

10:30 AM-11:30 AM

AI-Driven Shift-Left for Circuit and System Design
Xinfei Guo, Shanghai Jiao Tong University, China

High-Speed Ultra-Low Latency Mixed-Signal SerDes Transceiver Design Techniques for AI Computing Infrastructures
Xiaoyan Gui, Xi’an Jiaotong University, China

11:45 AM

Lunch

1:15 PM - 2:15 PM

AI for Analog IC Design Automation: Evolution and Open Challenges
Nuno Horta, University of Lisbon, Portugal

Clock Generation Techniques for High-Speed Wireline Transceivers
Hao Xu, Fudan University, China

2:15 PM - 3:15 PM

Bio-inspired Neuromorphic Olfaction: From Algorithms to Chips
Hong Chen, Tsinghua University, China

Clock and Data Synchronization Techniques for High-Performance Interconnection
Xiaoteng Zhao, Xidian University, China

3:15 PM

Tea Break (15 minutes)

3:30 PM - 4:30 PM

Product-Ready Neuromorphic MCU at the Sensor Edge
Amir Zjajo, Innatera Nanosystems B.V., the Netherlands

Design of Power-Efficient Reference-less PAM4 CDR for Ultra-High-Speed Wireline Communication
Zhao Zhang, Institute of Semiconductors, Chinese Academy of Sciences, China

4:30 PM - 5:30 PM

Reconfigurable Accelerator Design for Multi-Precision Floating-Point Computing: From Processing Elements to SME-Oriented Architectures
Wei Mao, Xidian University, China

Optical Receiver Front-Ends for AI Interconnect: Scenarios, Tradeoffs, and Design Guidelines
Dan Li, Xi’an Jiaotong University, China

5:30 PM - 6:00 PM

AI-Driven EDA: Reshaping Chip Design in the AI Era
Tran Thuy Vy, Cadence Vietnam

 

Tuesday, 15 September 2026
Moving to Ha Long Bay
Option 1: Free shutle bus departure: 2:00 PM at 144 Xuan Thuy Road, Cau Giay Ward, Hanoi (advanced registration is required)
Option 2: Day trip to visit Ha Long Bay on Cruise (participants pay the fee to our travel partner); hotel pickup at 7:15-8:00 AM

Day 1: Wednesday, 16 September 2026
Venue: Wyndham Legend Halong Hotel
Address: 12 Ha Long Street, Bai Chay Ward, Quang Ninh Province 02033

9:00 AM - 9:30 AM

Conference Opening & GC/TPC Reporting

9:30 AM - 10:30 AM

Keynote #1: From Design Automation to Autonomous Design: AI Super Agents for Chip Development
Ziyad Hanna
Corporate VP, System Design Verification and AI Technologies at Cadence Design Systems
Venue: Diamond 1
Chairs: Du Li, Nanjing University, China

10:30 AM

Tea Break (15 minutes)

11:00 AM - 12:00 AM

Keynote #2: Learning from Biology - Neuromorphic Techniques for an Intelligent Vision System: Using Obstacle Avoidance as an Example
Kea-Tiong (Samuel) Tang
National Tsing Hua University, Taiwan
Venue: Diamond 1
Chairs: Xuan-Tu Tran, Vietnam National University, Hanoi

12:00 PM

Lunch

1:30 PM - 2:45 PM

Session #1: AI Circuits and Systems for Robotics and Automation (4 papers)
Venue: Panorama 1
Chairs:  Yuhang Zhang, East China Normal University, China

Session #2: AI for Circuits and Systems I (5 papers)
Venue: Panorama 2
Chairs: Jinming Lu, Nanjing University, China

Session #3: Emerging applications: IoT, healthcare, smart factories, environment, robotics, autonomous vehicles, drones, AR/VR, metaverse I (4 papers)
Venue: Diamond 1
Chairs: Zhen Zhuang, The Chinese University of Hong Kong, China

Session #4:  Circuits and systems for AI I (5 papers)
Venue: Diamond 3
Chairs: HaiLong Jiao, PKU, China

2:45 PM

Tea Break (30 minutes)

3:15 PM - 4:15 PM

Session #5: Computer vision algorithms and architectures I (4 papers)
Venue: Panorama 1
Chairs: Duc-Tho Mai, Academy of Cryptography, Vietnam

Session #6 Special Session:  AI-Powered Electronic Design Automation for IC Design I (4 papers)
Venue: Panorama 2
Chairs: Bo Li, Xidian University, China

Session #7: AI for Future Wireless Communications (2 papers)
Venue: Diamond 1
Chairs: Yuhang Zhang, East China Normal University, China

Session #8 Special Session: Emerging Energy-Efficient Hardware and Computing Paradigms for Edge Intelligence I (4 papers)
Venue: Diamond 3
Chairs: Manh-Hiep Dao, VNU, Vietnam;

4:15 PM

Tea Break (15 minutes)

4:30PM - 6:00 PM

Session #9: Architecture for AI computing I (5 papers)
Venue: Panorama 1
Chairs:  Zhou Wang, Imperial Global Singapore of Imperial College London, Youngmin Kim, Hongik University, Korea

Session #10: Hardware/Software Co-Design and Design Automation for AI systems I (5 papers)
Venue: Panorama 2
Chairs: Yichuan Bai, Nanjing University, China

Session #11: Emerging computing devices and materials for AI (6 papers)
Venue: Diamond 1
Chairs: Hua Fan, UESTC, China

Session #12: In-Memory Computing I (5 papers)
Venue: Diamond 3
Chairs:  Bo Li, Xidian University, China

7:00 PM

Welcome reception
Shuttle buses will depart at the conference venue (the hotel’s lobby) from 18:00 to the restaurant.

Day 2: Thursday, 17 September 2026
Venue: Wyndham Legend Halong Hotel
Address: 12 Ha Long Street, Bai Chay Ward, Quang Ninh Province 02033

9:00 AM - 10:00 AM

Keynote #3: From FLOPS to Intelligence per Joule: The Case for Adaptive Dataflow
Tulika Mitra
National University of Singapore, Singapore
Venue: Diamond 1
Chairs: Duy-Hieu Bui, Vietnam National University, Hanoi

10:00 AM

Tea Break (30 minutes)

10:30 AM - 11:30 AM

Keynote #4: From Intelligence to Infrastructure: Building the Global Ecosystem for the Next AI Era
Hong-Viet Le
FPT Smart Cloud, Vietnam
Venue: Diamond 1
Chairs: Duy-Hieu Bui, Vietnam National University, Hanoi, Vietnam

11:45 AM

Lunch

1:15 PM - 2:30 PM

Session #13: Architecture for AI computing II (5 papers)
Venue: Panorama 1
Chairs: Thu-Huong Truong, HUST, Vietnam

Session #14: AI for Circuits and Systems II (5 papers)
Venue: Panorama 2
Chairs:  Jinming Lu, Nanjing Unverisity, China

Session #15 Circuits and systems for AI II (5 papers)
Venue: Diamond 1
Chairs: Manh-Hiep Dao, VNU, Vietnam

Session #16 Special Session: Specialized Hardware and Systems for Edge Large Language Model Acceleration and Application, Precision-Scalable and Reliability-Aware AI Circuits for Closed-Loop Edge Autonomy, Multimedia Systems and Applications for AI (4 papers)
Venue: Diamond 3
Chairs: Quang-Kien Trinh, LQDTU, Vietnam

2:30 PM

Tea Break (30 minutes)

3:00 PM - 4:00 PM

Session #17: Computer vision algorithms and architectures II (3 papers)
Venue: Panorama 1
Chairs: Qing Zhang, Shenzhen University, China

Session #18 Special Session: AI-Powered Electronic Design Automation for IC Design II (4 papers)
Venue: Panorama 2
Chairs: Thanh-Loan Pham Nguyen, HUST, Vietnam

Session #19 Special Session: Emerging Energy-Efficient Hardware and Computing Paradigms for Edge Intelligence II (4 papers)
Venue: Diamond 1
Chairs: Xueqing Li, Tsinghua University, China

Grand Challenge SS'25
Venue: Diamond 3
Chairs: Wei Mao, Xidian University, China

4:00 PM

Tea Break (15 minutes)

4:15 PM - 5:45 PM

Session #20: Emerging applications: IoT, healthcare, smart factories, environment, robotics, autonomous vehicles, drones, AR/VR, metaverse II (4 papers)
Venue: Panorama 1
Chairs: Quang-Kien Trinh, LQDTU, Vietnam

Session #21: Hardware/Software Co-Design and Design Automation for AI systems II (5 papers)
Venue: Panorama 2
Chairs: Zhen Zhuang, The Chinese University of Hong Kong

Session #22 Special Session: Compute-in-Memory Co-Design: From Emerging Devices to AI Application Optimization (5 papers)
Venue: Diamond 1
Chairs: Quoc-Hung Nguyen, VNU, Hanoi

Grand Challenge SS'26
Venue: Diamond 3
Chairs:  Wei Mao, Xidian University, China

7:00 PM

Banquet & Award Ceremony
Shuttle buses will depart at the conference venue (the hotel’s lobby) from 18:00 to the restaurant.

Day 3: Friday, 18 September 2026
Venue: Wyndham Legend Halong Hotel
Address: 12 Ha Long Street, Bai Chay Ward, Quang Ninh Province 02033

9:00 AM - 10:30 AM

Session #23: Neuromorphic and bioinspired circuits, processors, systems, and their applications I (5 papers)
Venue: Panorama 1
Chairs: Manh-Hiep Dao, VNU, Vietnam

Session #24: In-Memory Computing II (6 papers)
Venue: Panorama 2
Chairs: Duy-Hieu Bui, VNU, Hanoi, Vietnam

10:30 AM

Tea Break (15 minutes)

10:45 AM - 11:45 AM

Session #25: Neuromorphic and bioinspired circuits, processors, systems, and their applications II (6 papers)
Venue: Panorama 1
Chairs: Tran-Thuat Nguyen, VNU, Vietnam

Session #26 Special Session: Compute-in-Memory Co-Design: From Emerging Devices to AI Application Optimization II (4 papers)
Venue: Panorama 2
Chairs: Qing Zhang, Shenzhen University, China

12:15 PM

Lunch

1:30 PM - 5:15 PM

Workshop #1: The 2nd IEEE Chiplet Workshop on Circuits and Systems for Next-Generation AI Computing
Venue: Panorama 1
Chairs: Chixiao Chen, Fudan University, China; Anh Tuan Do, A*STAR, Singapore.

Industry talk: HiFloat Data Format Principles, Practices and Standards
Haonan Zhang, Huawei, China
Venue: Panorama 2
Chairs: Manh-Hiep Dao, VNU, Hanoi

Workshop #2: Smart Sensor Circuit and Intelligent Systems for Emerging Applications
Venue: Panorama 2
Chairs: Qing Zhang, Shenzhen University, China; Milin Zhang, Tsinghua University, China

5:15 PM

Closing